Power gating is a widely used technique to reduce power in integrated circuits due to increasing leakage power in deep submicron technologies. Some integrated circuits include a power gated region, also referred to as a power gated digital place and route region. A power gated region is a region of cells to which a power supply is switched, for example to which power can be turned on and off. A power gated region can be described as a plurality of cells in an integrated circuit having a switched power supply. After power is restored to a power gated region, it is desirable to detect whether the voltage level of the switched power supply has reached an operational level.
Typical CMOS logic gates have relatively low input threshold voltages: their outputs will switch to VDD as soon as their inputs rise above about 1-200 mV (depending on the CMOS process and doping) above a negative supply voltage (VSS) or ground (GND). Therefore, such known typical CMOS logic gates are not suitable as voltage level detection circuits. In addition, the voltage level of a switched power supply rises relatively slowly which can induce crowbar currents, consuming unnecessary power and reducing reliability.
Improvements in voltage detection approaches, such as in an integrated circuits using CMOS technology, are desirable.